Keys For Optimizing Efficient CMOS Architectures: Low Power Circuits Arithmetic Applications

Prices from
62.95

Featured

COMPARE ALL WEBSHOPS (2)

Description

Amazon Pages: 100, Paperback, LAP Lambert Academic Publishing
Description Description
Product Specifications Product specifications
Related results Related results
Next
Previous

Compare webshops (2)

Shop
Price
Amazon Logo
€ 62.95
To Shop
Amazon Marketplace Logo
€ 62.95
To Shop
Description (1)

Pages: 100, Paperback, LAP Lambert Academic Publishing

Product specifications

Brand LAP LAMBERT Academic Publishing
EAN
  • 9786208456115
MPN
  • Refer to Sapnet.

Editions Notre Savoir

Clés pour l'optimisation des architectures CMOS efficaces: Circuits à faible consommation applications arithmétiques

€ 62.02
Compare 2 stores 2 stores

CRC Press

Low Power Designs in Nanodevices and Circuits for Emerging Applications

€ 70.23
Compare 2 stores 2 stores

Independently Published

Mastering Low Power CMOS Circuits and VLSI Design: Step by Methods for...

€ 21.40
Compare 2 stores 2 stores

Springer

THz and Sub CMOS Electronics for High Speed Telecommunication: Architectures Circuits Future 6G Transceivers

€ 127.69
Compare 2 stores 2 stores
Featured Choice
€ 62.95
To Shop